(A) Field of the Invention
The present invention is related to a method of wear leveling for a non-volatile memory and a wear leveling apparatus using the same.
(B) Description of Related Art
A non-volatile memory device such as ATA solid state disk or SD flash memory card may have an internal mapping from the received logical addresses to physical addresses of a non-volatile memory. In order to wear each physical block of non-volatile memory equally, the mapping changes during the running time because the host may need more time to write some specific LBA (Logical Block Addressing) addresses than other addresses. As shown in FIG. 1, a logical address (LBA) from the host 11 is converted into a physical address or PBA (Physical Block Addressing) by an address converter 12. The physical address is used for data read/write for a non-volatile memory 13 such as a flash memory. The address converter 12 may include a RAM 14 storing the mapping of logical addresses and physical addresses for inquiry by the address converter 12.
The RAM storing the mapping is crucial to the cost. A larger RAM increases the cost. Moreover, the wear leveling algorithm may not obtain all mapping data at one time if the RAM size is not large enough. Therefore, if the storage capacity of the RAM is insufficient, a window may be established to resolve the problem.
As shown in FIG. 2, a non-volatile memory is divided by multiple block groups, and different groups correspond to different windows. For instance, the wear leveling algorithm processes Block Group 0 first, and RAM stores only window 0's mapping data, and then the wear leveling algorithm processes Block Group 1 and the RAM stores only window 1's mapping data. Consequently, the RAM size can be fixed, even if the amount of mapping increases with the larger non-volatile memory. However, this method can make only the number of program/erase in the same window consistent, while the program/erase quantities of different windows may still be unbalanced.